From 081117b326d0a5ee2b901074014ef8412dbf94f6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jo=C3=A3o=20Magalh=C3=A3es?= <joamag@gmail.com>
Date: Tue, 25 Apr 2023 09:59:07 +0100
Subject: [PATCH] chore: support for rom bank writing
---
src/mmu.rs | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mmu.rs b/src/mmu.rs
index 3584df47..245e95a6 100644
--- a/src/mmu.rs
+++ b/src/mmu.rs
@@ -277,8 +277,11 @@ impl Mmu {
// External RAM (8 KB)
0xa000 | 0xb000 => self.rom.write(addr, value),
- // Working RAM (8 KB)
- 0xc000 | 0xd000 => self.ram[(addr & 0x1fff) as usize] = value,
+ // Working RAM 0 (4 KB)
+ 0xc000 => self.ram[(addr & 0x0fff) as usize] = value,
+
+ // Working RAM 1 (Banked) (4KB)
+ 0xd000 => self.ram[(self.ram_offset + (addr & 0x0fff)) as usize] = value,
// Working RAM Shadow
0xe000 => self.ram[(addr & 0x1fff) as usize] = value,
--
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