From 269501198245ff81e72230f44e35007d26b18e52 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jo=C3=A3o=20Magalh=C3=A3es?= <joamag@gmail.com>
Date: Sun, 4 Jun 2023 19:39:00 +0100
Subject: [PATCH] fix: clippy fix
---
src/apu.rs | 2 +-
src/ppu.rs | 2 +-
src/timer.rs | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/apu.rs b/src/apu.rs
index dbbe2891..1e26fe1a 100644
--- a/src/apu.rs
+++ b/src/apu.rs
@@ -269,7 +269,7 @@ impl Apu {
return;
}
- self.sequencer += cycles as u16;
+ self.sequencer += cycles;
if self.sequencer >= 8192 {
// each of these steps runs at 512/8 Hz = 64Hz,
// meaning a complete loop runs at 512 Hz
diff --git a/src/ppu.rs b/src/ppu.rs
index 946f6ac4..7df9a923 100644
--- a/src/ppu.rs
+++ b/src/ppu.rs
@@ -598,7 +598,7 @@ impl Ppu {
// increments the current mode clock by the provided amount
// of CPU cycles (probably coming from a previous CPU clock)
- self.mode_clock += cycles as u16;
+ self.mode_clock += cycles;
match self.mode {
PpuMode::OamRead => {
diff --git a/src/timer.rs b/src/timer.rs
index 7adc5fd9..5e67e832 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -40,14 +40,14 @@ impl Timer {
}
pub fn clock(&mut self, cycles: u16) {
- self.div_clock += cycles as u16;
+ self.div_clock += cycles;
while self.div_clock >= 256 {
self.div = self.div.wrapping_add(1);
self.div_clock -= 256;
}
if self.tima_enabled {
- self.tima_clock += cycles as u16;
+ self.tima_clock += cycles;
while self.tima_clock >= self.tima_ratio {
// in case TIMA value overflows must set the
// interrupt and update the TIMA value to
--
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