diff --git a/frontends/sdl/src/main.rs b/frontends/sdl/src/main.rs index 8900eb0bd6355851581fd7a7459a286335e7d5d7..ea13c0f0d0ef86bfc28401cba28e37506f98cc8c 100644 --- a/frontends/sdl/src/main.rs +++ b/frontends/sdl/src/main.rs @@ -719,7 +719,7 @@ struct Args { )] cycles: u64, - #[arg(short, long, default_value_t = String::from("C:/Users/joamag/Desktop/gb-test-roms/dmg_sound/rom_singles/03-trigger.gb"), help = "Path to the ROM file to be loaded")] + #[arg(short, long, default_value_t = String::from("C:/Users/joamag/Desktop/gb-test-roms/dmg_sound/rom_singles/09-wave read while on.gb"), help = "Path to the ROM file to be loaded")] rom_path: String, } diff --git a/src/apu.rs b/src/apu.rs index cb8038c615f803cd9c5933dfff9bdad9eb8e7d51..c64ff9b4d5260dd4c49cf6b295facbb7265618ee 100644 --- a/src/apu.rs +++ b/src/apu.rs @@ -649,9 +649,7 @@ impl Apu { } // 0xFF30-0xFF3F — Wave pattern RAM - 0xff30..=0xff3f => { - self.wave_ram[addr as usize & 0x000f] = value; - } + 0xff30..=0xff3f => self.wave_ram[addr as usize & 0x000f] = value, _ => warnln!("Writing in unknown APU location 0x{:04x}", addr), } @@ -1007,8 +1005,7 @@ impl Apu { self.ch1_envelope_sequence = 0; self.ch1_sweep_sequence = 0; - let unfreeze = self.ch1_length_timer == 0; - if unfreeze { + if self.ch1_length_timer == 0 { self.ch1_length_timer = 64; if self.ch1_length_enabled && self.sequencer_step % 2 == 1 { self.tick_length(Channel::Ch1); @@ -1021,8 +1018,7 @@ impl Apu { self.ch2_timer = ((2048 - self.ch2_wave_length) << 2) as i16; self.ch2_envelope_sequence = 0; - let unfreeze = self.ch2_length_timer == 0; - if unfreeze { + if self.ch2_length_timer == 0 { self.ch2_length_timer = 64; if self.ch2_length_enabled && self.sequencer_step % 2 == 1 { self.tick_length(Channel::Ch2); @@ -1035,8 +1031,7 @@ impl Apu { self.ch3_timer = 3; self.ch3_position = 0; - let unfreeze = self.ch3_length_timer == 0; - if unfreeze { + if self.ch3_length_timer == 0 { self.ch3_length_timer = 256; if self.ch3_length_enabled && self.sequencer_step % 2 == 1 { self.tick_length(Channel::Ch3); @@ -1051,8 +1046,7 @@ impl Apu { self.ch4_lfsr = 0x7ff1; self.ch4_envelope_sequence = 0; - let unfreeze = self.ch4_length_timer == 0; - if unfreeze { + if self.ch4_length_timer == 0 { self.ch4_length_timer = 64; if self.ch4_length_enabled && self.sequencer_step % 2 == 1 { self.tick_length(Channel::Ch4); diff --git a/src/mmu.rs b/src/mmu.rs index c5bd6784c802790f20e6ad555a5233959e22dae3..e59fc25f2b2fee65a0a4712e22c30af4e51be274 100644 --- a/src/mmu.rs +++ b/src/mmu.rs @@ -9,7 +9,7 @@ use crate::{ ppu::Ppu, rom::Cartridge, serial::Serial, - timer::Timer, + timer::Timer, warnln, }; pub const BOOT_SIZE_DMG: usize = 256; @@ -340,7 +340,7 @@ impl Mmu { 0x00 } }, - 0x10..=0x26 | 0x30..=0x3f => self.apu.read(addr), + 0x10 | 0x20 | 0x30 => self.apu.read(addr), 0x40 | 0x60 | 0x70 => self.ppu.read(addr), 0x50 => match addr & 0x00ff { 0x51..=0x55 => self.dma.read(addr), @@ -448,7 +448,7 @@ impl Mmu { 0x04..=0x07 => self.timer.write(addr, value), _ => debugln!("Writing to unknown IO control 0x{:04x}", addr), }, - 0x10..=0x26 | 0x30..=0x3f => self.apu.write(addr, value), + 0x10 | 0x20 | 0x30 => self.apu.write(addr, value), 0x40 | 0x60 | 0x70 => { match addr & 0x00ff { // 0xFF46 — DMA: OAM DMA source address & start