From 3475fc6c91076f0c709014e990840c037e939360 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jo=C3=A3o=20Magalh=C3=A3es?= <joamag@gmail.com>
Date: Sun, 23 Jul 2023 03:11:11 +0100
Subject: [PATCH] chore: new waveform control

---
 frontends/sdl/src/main.rs |  2 +-
 src/apu.rs                | 16 +++++-----------
 src/mmu.rs                |  6 +++---
 3 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/frontends/sdl/src/main.rs b/frontends/sdl/src/main.rs
index 8900eb0b..ea13c0f0 100644
--- a/frontends/sdl/src/main.rs
+++ b/frontends/sdl/src/main.rs
@@ -719,7 +719,7 @@ struct Args {
     )]
     cycles: u64,
 
-    #[arg(short, long, default_value_t = String::from("C:/Users/joamag/Desktop/gb-test-roms/dmg_sound/rom_singles/03-trigger.gb"), help = "Path to the ROM file to be loaded")]
+    #[arg(short, long, default_value_t = String::from("C:/Users/joamag/Desktop/gb-test-roms/dmg_sound/rom_singles/09-wave read while on.gb"), help = "Path to the ROM file to be loaded")]
     rom_path: String,
 }
 
diff --git a/src/apu.rs b/src/apu.rs
index cb8038c6..c64ff9b4 100644
--- a/src/apu.rs
+++ b/src/apu.rs
@@ -649,9 +649,7 @@ impl Apu {
             }
 
             // 0xFF30-0xFF3F — Wave pattern RAM
-            0xff30..=0xff3f => {
-                self.wave_ram[addr as usize & 0x000f] = value;
-            }
+            0xff30..=0xff3f => self.wave_ram[addr as usize & 0x000f] = value,
 
             _ => warnln!("Writing in unknown APU location 0x{:04x}", addr),
         }
@@ -1007,8 +1005,7 @@ impl Apu {
         self.ch1_envelope_sequence = 0;
         self.ch1_sweep_sequence = 0;
 
-        let unfreeze = self.ch1_length_timer == 0;
-        if unfreeze {
+        if self.ch1_length_timer == 0 {
             self.ch1_length_timer = 64;
             if self.ch1_length_enabled && self.sequencer_step % 2 == 1 {
                 self.tick_length(Channel::Ch1);
@@ -1021,8 +1018,7 @@ impl Apu {
         self.ch2_timer = ((2048 - self.ch2_wave_length) << 2) as i16;
         self.ch2_envelope_sequence = 0;
 
-        let unfreeze = self.ch2_length_timer == 0;
-        if unfreeze {
+        if self.ch2_length_timer == 0 {
             self.ch2_length_timer = 64;
             if self.ch2_length_enabled && self.sequencer_step % 2 == 1 {
                 self.tick_length(Channel::Ch2);
@@ -1035,8 +1031,7 @@ impl Apu {
         self.ch3_timer = 3;
         self.ch3_position = 0;
 
-        let unfreeze = self.ch3_length_timer == 0;
-        if unfreeze {
+        if self.ch3_length_timer == 0 {
             self.ch3_length_timer = 256;
             if self.ch3_length_enabled && self.sequencer_step % 2 == 1 {
                 self.tick_length(Channel::Ch3);
@@ -1051,8 +1046,7 @@ impl Apu {
         self.ch4_lfsr = 0x7ff1;
         self.ch4_envelope_sequence = 0;
 
-        let unfreeze = self.ch4_length_timer == 0;
-        if unfreeze {
+        if self.ch4_length_timer == 0 {
             self.ch4_length_timer = 64;
             if self.ch4_length_enabled && self.sequencer_step % 2 == 1 {
                 self.tick_length(Channel::Ch4);
diff --git a/src/mmu.rs b/src/mmu.rs
index c5bd6784..e59fc25f 100644
--- a/src/mmu.rs
+++ b/src/mmu.rs
@@ -9,7 +9,7 @@ use crate::{
     ppu::Ppu,
     rom::Cartridge,
     serial::Serial,
-    timer::Timer,
+    timer::Timer, warnln,
 };
 
 pub const BOOT_SIZE_DMG: usize = 256;
@@ -340,7 +340,7 @@ impl Mmu {
                                 0x00
                             }
                         },
-                        0x10..=0x26 | 0x30..=0x3f => self.apu.read(addr),
+                        0x10 | 0x20 | 0x30 => self.apu.read(addr),
                         0x40 | 0x60 | 0x70 => self.ppu.read(addr),
                         0x50 => match addr & 0x00ff {
                             0x51..=0x55 => self.dma.read(addr),
@@ -448,7 +448,7 @@ impl Mmu {
                                 0x04..=0x07 => self.timer.write(addr, value),
                                 _ => debugln!("Writing to unknown IO control 0x{:04x}", addr),
                             },
-                            0x10..=0x26 | 0x30..=0x3f => self.apu.write(addr, value),
+                            0x10 | 0x20 | 0x30 => self.apu.write(addr, value),
                             0x40 | 0x60 | 0x70 => {
                                 match addr & 0x00ff {
                                     // 0xFF46 — DMA: OAM DMA source address & start
-- 
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