From 56ce6bc5e5e502c0406efde82042416a8e891d7e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jo=C3=A3o=20Magalh=C3=A3es?= <joamag@gmail.com>
Date: Sat, 25 Jun 2022 15:22:18 +0100
Subject: [PATCH] feat: initial registers support
---
src/cpu.rs | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/src/cpu.rs b/src/cpu.rs
index 6f2d5d0f..eea9197d 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -1,3 +1,5 @@
+const RAM_SIZE: usize = 8192;
+
pub struct Cpu {
pc: u16,
sp: u16,
@@ -9,9 +11,40 @@ pub struct Cpu {
reg_f: u8,
reg_h: u8,
reg_l: u8,
+ ram: [u8; RAM_SIZE],
}
impl Cpu {
+ pub fn new() -> Cpu {
+ Cpu {
+ pc: 0x0,
+ sp: 0x0,
+ reg_a: 0x0,
+ reg_b: 0x0,
+ reg_c: 0x0,
+ reg_d: 0x0,
+ reg_e: 0x0,
+ reg_f: 0x0,
+ reg_h: 0x0,
+ reg_l: 0x0,
+ ram: [0u8; RAM_SIZE],
+ }
+ }
+
+ pub fn clock(&mut self) {
+ // fetches the current instruction and increments
+ // the PC (program counter) accordingly
+ let instruction = self.ram[self.pc as usize];
+ self.pc += 1;
+
+ let opcode = instruction & 0xf000;
+ let address = instruction & 0x0fff;
+ let x = ((instruction & 0x0f00) >> 8) as usize;
+ let y = ((instruction & 0x00f0) >> 4) as usize;
+ let nibble = (instruction & 0x000f) as u8;
+ let byte = (instruction & 0x00ff) as u8;
+ }
+
#[inline(always)]
fn reg_af(&self) -> u16 {
(self.reg_a as u16) << 8 | self.reg_f as u16
--
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