From 593a20cb6f03f8e5a2c8ef9f6dcbcf2b2582aada Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jo=C3=A3o=20Magalh=C3=A3es?= <joamag@gmail.com>
Date: Sun, 26 Jun 2022 21:22:31 +0100
Subject: [PATCH] fet: more support for mmu and new opcode
---
src/cpu.rs | 7 ++++++-
src/mmu.rs | 23 +++++++++++++++++++++++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/src/cpu.rs b/src/cpu.rs
index 2b8d463a..edbf9447 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -69,7 +69,7 @@ pub const INSTRUCTIONS: [(fn(&mut Cpu), u8, &'static str); 208] = [
(nop, 4, "NOP"),
(nop, 4, "NOP"),
(nop, 4, "NOP"),
- (nop, 4, "NOP"),
+ (ld_a_u8, 8, "LD A, u8"),
(nop, 4, "NOP"),
// 0x4 opcodes
(nop, 4, "NOP"),
@@ -690,6 +690,11 @@ fn ld_mhld_a(cpu: &mut Cpu) {
cpu.set_hl(cpu.hl().wrapping_sub(1));
}
+fn ld_a_u8(cpu: &mut Cpu) {
+ let byte = cpu.read_u8();
+ cpu.a = byte;
+}
+
fn xor_a_a(cpu: &mut Cpu) {
cpu.a ^= cpu.a;
diff --git a/src/mmu.rs b/src/mmu.rs
index 2c163dc7..d2adbdd7 100644
--- a/src/mmu.rs
+++ b/src/mmu.rs
@@ -47,6 +47,29 @@ impl Mmu {
println!("WRITING TO RAM");
self.ram[(addr & 0x1fff) as usize] = value;
}
+ // Working RAM shadow
+ 0xe000 => {
+ println!("WRITING TO RAM Shadow");
+ self.ram[(addr & 0x1fff) as usize] = value;
+ }
+ // Working RAM shadow, I/O, Zero-page RAM
+ 0xf000 => match addr & 0x0f00 {
+ 0x000 | 0x100 | 0x200 | 0x300 | 0x400 | 0x500 | 0x600 | 0x700 | 0x800 | 0x900
+ | 0xa00 | 0xb00 | 0xc00 | 0xd00 => {
+ self.ram[(addr & 0x1fff) as usize] = value;
+ }
+ 0xe00 => {
+ println!("WRITING TO GPU OAM");
+ }
+ 0xf00 => {
+ if addr >= 0xff80 {
+ println!("WRITING TO Zero page");
+ } else {
+ println!("WRITING TO IO control");
+ }
+ }
+ addr => panic!("Writing in unknown location 0x{:04x}", addr),
+ },
addr => panic!("Writing in unknown location 0x{:04x}", addr),
}
}
--
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