From ce6c8df9c57fc700c910fed052bfd066707db2c2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jo=C3=A3o=20Magalh=C3=A3es?= <joamag@gmail.com>
Date: Thu, 7 Jul 2022 16:44:24 +0100
Subject: [PATCH] feat: new dma transfer
---
src/mmu.rs | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mmu.rs b/src/mmu.rs
index 360d7f95..a64f6a6a 100644
--- a/src/mmu.rs
+++ b/src/mmu.rs
@@ -175,10 +175,9 @@ impl Mmu {
0x0046 => {
// @todo must increment the cycle count by 160
// and make this a separated dma.rs file
- println!("GOING TO START DMA transfer to 0x{:x}00", value);
+ println!("Going to start DMA transfer to 0x{:x}00", value);
let data = self.read_many((value as u16) << 8, 160);
self.write_many(0xfe00, &data);
- println!("FINISHED DMA transfer");
}
_ => self.ppu.write(addr, value),
}
--
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