From f38e5714c27c5517a601ad5d5ae2aedbd085a1d4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jo=C3=A3o=20Magalh=C3=A3es?= <joamag@gmail.com>
Date: Sun, 25 Feb 2024 11:37:33 +0000
Subject: [PATCH] docs: more comments added
---
src/mmu.rs | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mmu.rs b/src/mmu.rs
index 082cba81..67342609 100644
--- a/src/mmu.rs
+++ b/src/mmu.rs
@@ -271,7 +271,7 @@ impl Mmu {
// @TODO: Implement DMA transfer in a better way, meaning that
// the DMA transfer should respect the timings
-
+ //
// In both Normal Speed and Double Speed Mode it takes about 8 μs
// to transfer a block of $10 bytes. That is, 8 M-cycles in Normal
// Speed Mode [1], and 16 “fast” M-cycles in Double Speed Mode [2].
@@ -279,6 +279,8 @@ impl Mmu {
// to support General Purpose or HBlank DMA, that’s because there are
// always 2 bytes transferred per microsecond (even if the itself
// program runs it Normal Speed Mode).
+ //
+ // we should also respect General-Purpose DMA vs HBlank DMA
// only runs the DMA transfer if the system is in CGB mode
// this avoids issues when writing to DMG unmapped registers
--
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