Allows modularity and extendability in Zippy.

Allowing better error detection and faster execution (hardware accelerated).

This allows both aarch64 and sse4.2 implementations.

This should improved performance by 200%.

Intel implementation uses a different polynomial (CRC-32/ISCSI or CRC32-C (Castagnoli)) so I had to remove the support.

Uses hardware acceleration if available, otherwise falls back to software implementation.

Includes strong header which includes CRC32.

Also simplified error to string conversion.

This approach avoids many of the possible panics.

Made read MMU a non mutable operation.
Added support for CPU description.
Added Display support for CPU.
Extracted type definition for `Instruction`.
Support for diag_gb!() - uses global unsafe approach, which is not problematic for the purpose.
Inline fetch() operation in cpu clock.
Moved pedantic validation up in the CPU.
Fix simple diag issue.
Changed naming of read and write unsafe ops to raw.
New pedantic asserts.
Fix an issue with HDMA destination address prevent CHIP-8 ROM from
working.