Allow future proof extendability of the feature payload.

Allows modularity and extendability in Zippy.

Allowing better error detection and faster execution (hardware accelerated).

This allows both aarch64 and sse4.2 implementations.

This should improved performance by 200%.

Intel implementation uses a different polynomial (CRC-32/ISCSI or CRC32-C (Castagnoli)) so I had to remove the support.

Uses hardware acceleration if available, otherwise falls back to software implementation.

Includes strong header which includes CRC32.

Also simplified error to string conversion.

This approach avoids many of the possible panics.