fet: more support for mmu and new opcode

src/cpu.rs

@@ -69,7 +69,7 @@ pub const INSTRUCTIONS: [(fn(&mut Cpu), u8, &'static str); 208] = [
     (nop, 4, "NOP"),
     (nop, 4, "NOP"),
     (nop, 4, "NOP"),
-    (nop, 4, "NOP"),
+    (ld_a_u8, 8, "LD A, u8"),
     (nop, 4, "NOP"),
     // 0x4 opcodes
     (nop, 4, "NOP"),
@@ -690,6 +690,11 @@ fn ld_mhld_a(cpu: &mut Cpu) {
     cpu.set_hl(cpu.hl().wrapping_sub(1));
 }
 
+fn ld_a_u8(cpu: &mut Cpu) {
+    let byte = cpu.read_u8();
+    cpu.a = byte;
+}
+
 fn xor_a_a(cpu: &mut Cpu) {
     cpu.a ^= cpu.a;
 

src/mmu.rs

@@ -47,6 +47,29 @@ impl Mmu {
                 println!("WRITING TO RAM");
                 self.ram[(addr & 0x1fff) as usize] = value;
             }
+            // Working RAM shadow
+            0xe000 => {
+                println!("WRITING TO RAM Shadow");
+                self.ram[(addr & 0x1fff) as usize] = value;
+            }
+            // Working RAM shadow, I/O, Zero-page RAM
+            0xf000 => match addr & 0x0f00 {
+                0x000 | 0x100 | 0x200 | 0x300 | 0x400 | 0x500 | 0x600 | 0x700 | 0x800 | 0x900
+                | 0xa00 | 0xb00 | 0xc00 | 0xd00 => {
+                    self.ram[(addr & 0x1fff) as usize] = value;
+                }
+                0xe00 => {
+                    println!("WRITING TO GPU OAM");
+                }
+                0xf00 => {
+                    if addr >= 0xff80 {
+                        println!("WRITING TO Zero page");
+                    } else {
+                        println!("WRITING TO IO control");
+                    }
+                }
+                addr => panic!("Writing in unknown location 0x{:04x}", addr),
+            },
             addr => panic!("Writing in unknown location 0x{:04x}", addr),
         }
     }