Adds this CPU speed print support to the web debug panel.

With initial approach for scalling down the speed of other components.

Allows the transfer of data according to the specs in dma.rs.

This is only a structure change and no real DMA implementation has been done.

The performance should be poor as there're lots of if clauses.

This is a temporary hack until a real speed switch is available.

The double speed mode is still not available.

Allows usage of tiles from multiple VRAM banks.

Created more panic conditions for the KEY0 and KEY1.

Still requiring a lot of operational work to allow proper working.

This was causing Boot to fail for CGB.

There's already two drivers implemented: Null and Print (to stdout).

The complete GB, CPU and MMU linking is done.

This issue was prevent CH4 from working properly.
Also added TODO operations to the master volume.

Still requires work to be able to be able to emulate APU together with the CPU instead of inverting the control.