With initial approach for scalling down the speed of other components.

Allows the transfer of data according to the specs in dma.rs.

This is only a structure change and no real DMA implementation has been done.

This is a temporary hack until a real speed switch is available.

The code now breaks if pedantic is set and a warning is triggered.

There's already two drivers implemented: Null and Print (to stdout).

The complete GB, CPU and MMU linking is done.

Still requires work to be able to be able to emulate APU together with the CPU instead of inverting the control.

Made test on inst timing pass